Heretofore, there is a card type electronic device referred to as a PC card, and there is realized the device equipped with various types of functions for expansion of a function of a portable personal computer or the like. There are a communication card, a memory card and the like of a modem, an LAN, a radio telephone and the like. These PC cards are used by being attached to a host device (e.g., the portable personal computer).
The PC card includes: a first in first out (FIFO) memory as a buffer in transmitting and receiving data between the card and a CPU of the host device; and an interface circuit which controls an access to this FIFO memory. Moreover, a data communication speed can be matched between the card and the CPU of the host device via the FIFO memory.
In a conventional procedure in a case where data is sent from the host device to the PC card via the above FIFO memory, first the host device divides transmission data into a certain amount (e.g., 16 bytes) of the data, and one of the divided data is written into the FIFO memory. Next, when this write is detected, the interface circuit of the FIFO memory generates an interrupt signal in order to notify the CPU of the PC card that there is the data in the FIFO memory. Next, in this interrupt processing, the CPU of the PC card reads data from the FIFO memory. Next, when this read is detected, the interface circuit of the FIFO memory outputs a readout completion notice signal to the host device. In response to this readout completion notice, the CPU of the host device writes the next data into the FIFO memory, if any.
As described above, heretofore, the host device divides the transmission data into the certain amount of the data, and repeats the above procedure every divided data to thereby transmit the data to the PC card.
Moreover, to reduce a load on the CPU in reading the data from the FIFO memory, an FIFO memory provided with a count function is known which generates the interrupt signal in a case where the amount of the data stored in the FIFO memory reaches a predetermined amount (see, e.g. Patent Document 1).    [Patent Document 1] Japanese Patent Application Laid-Open No. 6-325565 (Page 2, FIG. 1)
In recent years, in the FIFO memory mounted on the PC card, capacity enlargement is possible. Accordingly, when the amount of the data to be sent from the host device to the PC card once is increased in accordance with the maximum storage capacity of the FIFO memory, the number of the divided transmission number decreases. Therefore, it is possible to reduce the number of generated interrupt times with respect to the CPU of the PC card. Moreover, it is possible to increase the amount of the data to be handled in one interrupt processing. Therefore, the loads due to the interrupt processing are reduced, and the data can integrally be processed efficiently. Owing to these factors and the like, a processing speed can be enhanced.
However, for this purpose, the existing communication control program to be executed by the CPU of the host device needs to be changed to adapt the amount of the data to be sent from the host device to the PC card once in accordance with the new FIFO memory. Every time the FIFO memory to be mounted on the PC card is version-upgraded, the communication control program for the host device is changed in accordance with the new FIFO memory. This is a factor for cost increase, and additionally factors for defects such as bugs are increased. For such a reason, there is a demand for diversion of the existing communication control program for the host device.
For the similar reason, as to the above FIFO memory provided with the count function, unless the communication control program for the host device is changed, the effect of the memory cannot be obtained, and therefore the memory is not easily applied.